Êèǹ·Õè˹Öè§ ÀÒ¾ÃÇÁ º··Õè 1 º·¹Ó º··Õè 2 ÇÔÇѲ¹Ò¡Òâͧ¤ÍÁ¾ÔÇàµÍÃìáÅлÃÐÊÔ·¸ÔÀÒ¾ Êèǹ·ÕèÊͧ Ãкº¤ÍÁ¾ÔÇàµÍÃì º··Õè 3 ÀÒ¾ÁØÁ¡ÇéÒ§¢Í§Ë¹éÒ·ÕèáÅСÒÃàª×èÍÁµèÍÀÒÂã¹à¤Ã×èͧ¤ÍÁ¾ÔÇàµÍÃì º··Õè 4 ˹èǤÇÒÁ¨Ó CACHE º··Õè 5 ˹èǤÇÒÁ¨ÓÀÒÂã¹ º··Õè 6 ˹èǤÇÒÁ¨ÓÀÒ¹͡ º··Õè 7 ¡ÒùӢéÍÁÙÅà¢éÒáÅСÒÃÊ觢éÍÁÙÅ º··Õè 8 ¡ÒÃʹѺʹع¢Í§Ãкº»¯ÔºÑµÔ¡Òà Êèǹ·ÕèÊÒÁ ˹èÇ»ÃÐÁÇżšÅÒ§ º··Õè 9 ÇÔ¸Õ¡Òäӹdz·Ò§¤³ÔµÈÒʵÃì¢Í§à¤Ã×èͧ¤ÍÁ¾ÔÇàµÍÃì º··Õè 10 ¤Ø³ÅѡɳÐáÅÐ˹éÒ·Õè¢Í§ Instruction Sets º··Õè 11 ªØ´¤ÓÊÑè§à¤Ã×èͧ : ÀÒÇСÒáÓ˹´·ÕèÍÂÙèáÅÐÃٻẺ º··Õè 12 â¤Ã§ÊÃéÒ§áÅÐ˹éÒ·Õè¢Í§«Õ¾ÕÂÙ º··Õè 13 ¤ÍÁ¾ÔÇàµÍÃìµÃСÙÅ RISC + http://www.it.nrru.ac.th/krit/410502/ + http://www.williamstallings.com/ComputerOrganization/ + https://www.pearsonhighered.com + Resource : 1 - 7 | 8 - 14 | 15 - 21
º··Õè 1 ¾×鹰ҹʶһѵ¡Â¡ÃÃÁ¤ÍÁ¾ÔÇàµÍÃì º··Õè 2 ¢éÍÁÙÅ (Data) º··Õè 3 ¡Òäӹdz·Ò§¤³ÔµÈÒʵÃì ˹èÇ»ÃÐÁÇżŷҧ¤³ÔµÈÒʵÃì (ALU) º··Õè 4 ªØ´¤ÓÊÑè§ (Instruction Sets) º··Õè 5 ¡ÒÃÍ͡Ẻâ»Ãà«Êà«ÍÃì (Processor Design) º··Õè 6 Pipeline, Scalar & vector Processor º··Õè 7 ˹èǤÇÒÁ¨ÓËÅÑ¡ (Main Memory) º··Õè 8 ᤪáÅÐ˹èǤÇÒÁ¨ÓàÊÁ×͹ (Cache and Virtual Memory) º··Õè 9 Ê×èͨѴà¡çº¢éÍÁÙÅ (Mass Storage) º··Õè 10 ºÑÊáÅÐÍÔ¹à·ÍÃìà¿« (Bus and Interface) º··Õè 11 ˹èǹÓà¢éÒáÅÐáÊ´§¼ÅÅѾ¸ì (Input / Output) º··Õè 12 ˹èǤǺ¤ØÁáÅÐàÊé¹·Ò§¢éÍÁÙÅ (Control Unit and Data Path) º··Õè 13 ¡ÒÃÊ×èÍÊÒà à¤Ã×Í¢èÒ áÅÐÍÔ¹à·ÍÃìà¹çµ (Communication, Networks and Internet) º··Õè 14 Multiprocessors º··Õè 15 Ãкº»¯ÔºÑµÔ¡Òà (Operating Systems) + http://dusithost.dusit.ac.th/~phorramatpanyaprat_ton/course/C4122701/c4122701.html + ÃÇÁÊäÅ´ì »ÃСͺ¡ÒÃÊ͹µÒÁËÑÇ¢éÍã¹Ë¹Ñ§Ê×Í